1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device provided in such a manner that nonvolatile variable resistive elements each having a first electrode, a second electrode, and a variable resistor of a metal oxide film sandwiched by the electrodes are arranged in the form of a matrix, and more particularly it relates to a nonvolatile semiconductor memory device provided with a cross-point type memory cell array having a 1R structure in which the variable resistive element has rectifying properties.
2. Description of the Related Art
In tandem with the penetration of a mobile device such as a portable electric device, a flash memory has been widely used as a large-capacity and inexpensive nonvolatile memory which can hold stored data even when it is powered off. However, recently it has been found that the flash memory is limited in its miniaturization, so that nonvolatile memories such as a MRAM (Magnetoresistive Random Access Memory), a PCRAM (Phase Change Random Access Memory), a CBRAM (Conductive Bridging Random Access Memory), and a RRAM (Resistive Random Access Memory (Refer to A. Sawa, “Resistive switching in transition metal oxides”, Material Today, Vol. 11, No. 6, p. 28-36 (2008) (hereinafter, referred to as the well-known document 1)) are increasingly being developed. Among these nonvolatile memories, the RRAM is a resistance change type nonvolatile memory using a change in deficient oxygen in a metal oxide, and it can implement a large resistance change and high-speed writing with a simple memory structure, so that it offers promising prospects as a highly integratable memory.
A unit element of the RRAM is composed of a two-terminal variable resistive element (resistance change element) in which a metal oxide film is sandwiched by two electrodes. Regarding the memory using the two-terminal variable resistive element, a cell structure and a memory array structure each having a simplest structure and suitable for increasing capacity are implemented in a cross-point type memory having a 1R structure in which a unit memory cell is only formed of a variable resistive element, as shown in Japanese Unexamined Patent Publication No. 2003-068984 (hereinafter, referred to as the well-known document 2). This structure can be provided in the RRAM having a large resistance change rate, but it is necessary to take measures against a leak current.
In order to eliminate the leak current in the 1R structure (having a variable resistive element only), a circuit is provided to prevent a voltage applied to the variable resistive element from fluctuating in view of load resistance on the side of a decoder when the voltage is applied to the variable resistive element according to Japanese Unexamined Patent Publication No. 2006-155846 (hereinafter, referred to as the well-known document 3). This is provided to take measures against the leak current in the 1R structure which is generated because the load resistance on the decoder side is not negligible as compared with resistance of the variable resistive element. That is, an externally applied voltage is divided based on a ratio between the resistance of the variable resistive element and the load resistance on the decoder side, so that a potential difference is generated between wirings connected to the variable resistive elements in a memory cell array, depending on a resistance value of each variable resistive element, which causes the leak current. In the configuration shown in the well-known document 3, the potential fluctuation between the wirings is prevented and the leak current is prevented by providing the circuit to detect the potential fluctuation between the wirings and to keep the voltage applied to the variable resistive elements constant.
However, the leak current can be prevented to a certain degree by this method, but in order to effectively prevent the leak current, it is necessary to reduce the number of the elements to the relatively small number in the memory cell array, so that area occupied by the decoder increases, and a memory chip size cannot be reduced.
Thus, to avoid the problem of the leak current, a cell structure called a 1T1R or 1D1R in which a current limit element such as a transistor or a two-terminal rectifying element (diode or varistor) is added to the unit memory cell has been developed as disclosed in Japanese Unexamined Patent Publication No. 2004-087069 (hereinafter, referred to as the well-known document 4). The 1T1R structure can control an amount and a direction of a current flowing in the variable resistive element in a 1R part and it is superior in controllability, but it is large in area and a multilayer structure cannot be easily provided, so that its memory capacity is limited by a chip area and a design rule.
Meanwhile, the 1D1R structure is provided such that a minimum area unit element is formed in a cross-point structure by optimizing the process, and multilayer structure can be provided, so that it is suitable for increasing capacity. The memory cell using the 1D1R structure can be combined with the matrix-shaped array structure as shown in the well-known document 2. However, to form the unit memory cell by connecting the variable resistive element and the two-terminal rectifying element in series, it is necessary to laminate a pn junction or Shottky junction and the variable resistive element, so that production steps become complicated.
In addition, in most cases, the variable resistive element in the RRAM shifts between the high resistance state and the low resistance state when different voltages having positive and negative polarities are applied across its electrodes. In order to satisfy the characteristics of the resistance change element and rectifying properties in the cross-point memory, it is required for the resistance to largely differ by the different polarities such as the positive voltage and the negative voltage, and for the resistance state to shift due to the application of the voltages having different polarities. Therefore, it is difficult to optimize characteristic balance of both variable resistive element and the rectifying element to obtain a preferable memory action.
Meanwhile, as for the metal oxide film having the perovskite structure such as Pr1-XCaXMnO3 or Sm1-XCaXMnO3, the fact that when one side of the film is formed into Shottky junction, characteristics satisfying both rectifying properties and properties of the variable resistive element can be obtained is disclosed in the well-known document 1. The device disclosed in Japanese Patent No. 4251576 uses the above characteristics and has an extremely simple structure in which a metal oxide film serving as the variable resistor is sandwiched by metal electrodes, and when the metal oxide film forms the Shottky junction with any one of the two electrodes, the same characteristics as that of the cross-point memory having the 1D1R structure disclosed in the well-known document 4 can be obtained with the cross-point memory having the 1R structure and a memory array in which a leakage current is prevented can be realized.
However, even in the similar structure, the rectifying properties are hardly generated and the above characteristics cannot be obtained in some cases, so that to satisfy constant material properties and a structural condition is considered necessary in order to obtain desired characteristics, but the condition have not been known yet.